Flexible I/O Configuration Thanks to FPGA Technology
The USM™ concept allows to realize even unusual I/O combinations on very small space for moderate volumes and at low cost. For this purpose, the P699 main XMC comes with a Cyclone™ III FPGA with 24,624 LE, and the conduction-cooled P598 main PMC features a Cyclone™ II with 33,216 LE. P699 and P598 get their specific function through the choice of the desired IP cores. This function can be changed at any time through the use of different IP cores, without any hardware modifications to the main module. The corresponding line drivers are implemented on a submodule which must be designed individually for each application and which is plugged onto the main XMC or main PMC. The main module also has 32 MB of DDR2 SDRAM main memory and up to 4 MB Flash memory in case the soft CPU, which is already implemented, is used.
Apart from enormous flexibility the usage of IP cores also has the benefit to provide independence from availability and allowed operation temperatures of components. This allows unlimited, guaranteed long-term delivery and application at up to -40 to +85 °C without any problems.
USM™ Development Package for Faster Time-to-Market
Using a comprehensive USM™ development package the user can turn his individual I/O requirements into production-ready products easily and quickly. The package includes a main PMC with a USM™ submodule, test hardware and an FPGA package with a Nios® CPU, memory control, connection to the PMC, Avalon®/Wishbone bridges and detailed documentation. For development of IP cores on the standard Wishbone bus the Wishbone Bus Maker tool from MEN is included. In order to use the Nios® core and to develop IP cores on the Avalon® bus you also need Altera®’s Quartus® II design environment including the SOPC builder.
For users who prefer a ready-to-use product MEN offers design and implementation of IP cores, design of the USM™ submodules as well as production of main modules and submodules.
