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  Editor's Choice  Failsafe OpenVPX switch bridges Gen 2 RIO and Ethernet
Editor's Choice

Failsafe OpenVPX switch bridges Gen 2 RIO and Ethernet

Chris A. Ciufo, Editor, OpenSystems MediaChris A. Ciufo, Editor, OpenSystems Media—October 7, 20100
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Remember all the fuss about RapidIO during the “fabric wars” five years ago? Yours truly predicted RapidIO would emerge a winner. It has (though not as I predicted), and it forms the internal backbone of ultra-high performance mission computers. Curtiss-Wright Controls Embedded Computing is capitalizing on RapidIO’s direct memory-mapped robustness in the VPX6-6902. This single-slot 6U board supports many OpenVPX profiles and configurations, but bridges RapidIO to multiple Ethernet ports. This offers the best of both worlds: inter- and intra-box switching using the best fabric for the job, be it GbE or Gen 2 RapidIO.

Supporting Gen-1 Serial RapidIO (1.25, 2.5, and 3.125 Gbaud) and Gen-2 (5.0 and 6.25 Gbaud), the switch has 28 four-lane ports. A typical configuration is 24x Serial RapidIO (x4) to the VPX backplane and 4x Serial RapidIO (x4) to the front with no Ethernet switching. But there are also 16x SERDES GbE and 2x 1000BASE-T ports to the backplane, along with 2x 10GbE and 1x 1000BASE-T to the front. Another board configuration might be 20x Serial RapidIO (x4) to the backplane, 4x Serial RapidIO (x4) to the front, along with 16x SERDES GbE and 2x 1000BASE-T to the rear with an additional 2x 10 GbE and one 1000BASE-T to the front. That’s a lot of I/O routing, all thanks to OpenVPX. As always, the board is available in air- and conduction-cooled rugged versions (though some I/O may be limited in conduction-cooled variants).

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