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Santa Clara, CA – January 29, 2009 – At the Real Time Embedded Computing Conference, TEK Microsystems, Incorporated, the leading supplier of VXS-based digitizers, has announced the new QuiXilica Tarvos-V5 VXS. This 6U ANSI/VITA 41 (VXS) compliant high-speed digitizer board combines high density FPGA processing with six 16-bit A/D input channels at 185 Msps (Megasamples per second) along with a coherent 16-bit D/A output channel.
By employing three Xilinx Virtex®-5 FPGAs, the Tarvos-V5 offers unmatched FPGA processing density per channel, along with a measured signal-to-noise ratio (SNR) of 72 dBFS and Spurious Free Dynamic Range (SFDR) in excess of 95 dB, making it suitable for high channel count signal processing for a wide range of applications such as RADAR, signals and electronic intelligence (SIGINT / ELINT), and Electronic Warfare (EW).
“The Tarvos-V5 is based on Tekmicro’s QuiXilica V5 Architecture which leverages a holistic design philosophy across all of our Xilinx Virtex®-5 based products. In addition to FPGA density, the Tarvos-V5 also delivers the industry’s highest analog signal fidelity”, reports Paul Martino, vice president of sales and marketing at TEK Microsystems, Inc. “As the latest in Tekmicro’s QuiXilica-V5 family of digitizers, Tarvos-V5 has captured the attention of our customers in the signals intelligence area, both for new programs and for technology refresh and upgrades of existing QuiXilica systems using Xilinx Virtex II Pro technology.”
Tarvos-V5 Reduces System Size by 30%
Many advanced signal processing applications are based on antenna array processing and require large numbers of channels and distributed signal processing. The architecture of the Tarvos-V5 combines six analog input channels with three Xilinx Virtex-5 FPGAs, providing up to 2,336 DSP slices and 1.285 TeraMAC/s of signal processing, equivalent to 61% of a Xilinx Virtex-5 SX95T device per input channel. For high channel count requirements such as beamforming, direction finding, jamming or anti-jam / interference cancellation, common in RADAR, SIGINT, communications, and EW applications, the Tarvos-V5 provides both the highest processing density per channel and per 6U slot, reducing total size, weight and power for many systems.
For example, in a phased array processor system with 20 I/Q inputs, where one FPGA is assigned to process data for each I/Q input channel set, a traditional PMC or XMC based architecture would require 10 or even 20 slots depending on SBC selection and FPGA requirements. The same system can be implemented in 7 slots using the Tarvos-V5 VXS, using less space and power but still providing the same number of channels and 40% more FPGA processing capability than a 10 slot XMC-based system with 20 XMC modules using SX95T FPGAs.
Tarvos-V5 Overview
Designed to meet the needs of demanding sensor-processing applications across a range of environments, the Tarvos-V5 employs three Xilinx Virtex®-5 FPGAs, advanced DDR3 SDRAM, and the highest resolution digital-to-analog and analog-to-digital converter technologies available at a 185 Msps sampling rate.
Each analog input channel uses a Linear Technology LTC2209 16-bit A/D converter, which is designed for digitizing high frequency, wide dynamic range signals within an analogue input bandwidth of 700 MHz. A range of options are available for input signal conditioning to support different receiver applications.
The output channel uses a Maxim MAX5891 16-bit D/A converter that is synchronized to the input clock rate. The output is AC coupled with full scale output voltage of -2 dBm into a 50 ohm load. The layout has been carefully designed to ensure phase matching of the clock across all input channels and to minimize aperture jitter. Trigger input and output connections are also provided on the front panel to allow the hardware to be employed in a variety of scenarios.
The Tarvos-V5 also features high bandwidth, low latency interconnect paths between its FPGAs which has been carefully specified to ensure that data from any analog channel can be broadcast to all FPGAs to support processing that relies on simultaneous access to data from all channels. This offers significant throughput advantages for a range of advanced multi-channel processing algorithms found in applications such as direction finding, STAP (Space Time Adaptive Processing) RADAR and Synthetic Aperature Radar (SAR) Image Formation.
For offboard communication, the Tarvos-V5 employs the latest flexible I/O communication modules (SFP+ and QSFP). Firmware and software support for a range of open standards and protocols, including Gigabit Ethernet, Serial FPDP (ANSI/VITA 17.1) and Xilinx Aurora, are available as part of the QuiXilica™ Developer’s Kit.
The Tarvos-V5 is available for a wide range of operating environments, including commercial grade as well as rugged air and conduction cooled to support deployed applications such as unmanned airborne, naval and ground vehicles.
In addition to the Tarvos-V5, Tekmicro offers a broad range of Xilinx Virtex-5 based streaming I/O and FPGA processing solutions for both analog and digital I/O in a range of form factors.
The Tarvos-V5 VXS is available now, with delivery from stock to 8 weeks ARO.
For more information visit the QuiXilica Tarvos-V5 VXS page.
About TEK Microsystems, Incorporated.
Founded in 1981 and headquartered in Chelmsford, Massachusetts, Tekmicro designs, manufactures and delivers a wide range of advanced high-performance boards and systems for embedded real-time data acquisition, data conversion, storage and recording. The Company provides both commercial and rugged grade products which are used in real-time systems designed for applications such as reconnaissance, electronic warfare, signals intelligence, mine detection, medical imaging, radar, sonar, semiconductor inspection and seismic research.