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| VMETRO FPE650 Quad Xilinx Virtex-5 FPGA VPX Processor Board with Dual FMC Sites |
VMETRO, a leader in embedded computing solutions based on standards such as VXS and XMC that utilize multi-gigabit serial interconnects, today announced one of the industrys first FPGA processing engines with support for the new FPGA Mezzanine Card (FMC/VITA 57) standard. The FPE650s innovative design integrates four Xilinx® Virtex®-5 FPGAs with two FMC I/O sites and VPX high-speed serial backplane connectivity, allowing I/O and processing capabilities in a single 6U slot. The FPE650, available in air-cooled and conduction-cooled rugged versions, is designed to tackle the most demanding digital signal processing applications such as Electronic Counter Measures (ECM), Signal Intelligence (SIGINT) and Electro-Optics (EO).
At the heart of the FPE650 are four fully inter-connected user programmable Xilinx Virtex-5 FPGAs. The FPGAs sites can be fitted with Virtex-5 SX95T, LX155T or FX100T platforms enabling the FPE650 to be optimized for DSP or logic centric designs. Each FPGA has four directly connected banks of memory to maximize performance. Two of the FPGAs interface to four banks of 9 Mbytes QDR2 SRAM memory; the other two FPGAs interface to two banks of 9 Mbytes QDR2 SRAM memory and two banks of 640 Mbytes DDR2 SDRAM memory.
“The balance of processing performance, modular I/O and VPX connectivity is very important for demanding applications. The FPE650 excels at this by allowing sensor I/O or system data to be delivered directly to the FPGAs.” comments Thomas Nygaard, Chief Technology Officer of VMETRO. “The FPE650 is pioneering use of the new FMC I/O mezzanine standard, opening the door for a whole new generation of products, such as ADC and DACs, tightly integrated into the FPGA resources of the carrier board without the overhead of protocol translation required by other mezzanine standards.”
The FPE650 addresses the I/O and data bandwidth requirements of high performance digital signal processing applications with three interconnects features – through FPGA Mezzanine Card (FMC/VITA 57) sites for front panel I/O, through a non-blocking crossbar to help optimize the FPGA topology, and VPX/VITA 46 connections for backplane I/O. For front panel I/O, each FMC site has 68 differential signal pairs supporting 2Gb/sec data rates per pair and four full duplex multi-Gigabit/sec connections to enable very large amounts of data to be moved between FMC modules and the on-board FPGAs. For on-board data movement, high-speed serial links from the FMC sites, the FPGA, and the backplane are routed to a non-blocking crossbar switch. By configuring the crossbar switch, the connections between these resources to be configured specifically to meet application needs. For backplane I/O, each FPGA has two x4 full duplex multi-Gigabit/sec serial ports routed to the VPX backplane with each x4 port able to move over 1 Gigabyte/sec of data. The FPE650 also provides backplane parallel I/O directly connected to two of the FPGAs.
“VMETRO is one of the first COTS vendors to announce products based on the new FMC standard. The combination of high-speed I/O FMC modules with our latest Virtex-5 SXT FPGA technology makes the FPE650 a very attractive product for a variety of DSP applications”, states Raj Seelam, DSP Solutions product manager at Xilinx. “The flexibility afforded by the industry-standard FMC specification will greatly enhance the ability of Xilinx and our partners in bringing more focused and comprehensive solutions to the high-performance marketplace.”
A Software and HDL development suite for the FPE650 is provided by VMETRO, including IP blocks such as DMA and memory controllers and sophisticated examples and utilities for FPGA configuration and development. The majority of the resources on all the FPGAs are available for user applications.
VMETRO will be announcing a range of FMC modules shortly to be used with the FPE650 and other VMETRO FPGA-based products.