Kim Clohessy was a founding vice president of Dy 4 Systems in Ottawa, where he was recruited from Bell Northern Research. Dy 4 Systems, which was formed in 1979, specialized in the design and manufacture of high-end VMEbus open architecture computer systems for the aerospace and defense industry.

Kim helped Dy 4 Systems grow successfully before leaving in 1992 to move to Scottsdale, Arizona, as a consultant for Ottawa-based Object Technologies and as vice president of Embedded Systems at IBM. In 2000 he transferred to Perth, Australia, where he soon resigned from IBM to form a new company.

During the early 1990s, Kim did much of the heavy lifting in terms of editing the work being done on the second generation of the VMEbus specification. He was an avid sailor and diver who enjoyed sailing and racing on the Swan River and the Indian Ocean.

Kim passed away in 2006 at 52 years of age, after a short battle with melanoma.

Key contributions

• 1990: Kim joined Doug Patterson as Mil-Spec Study Group co-chair.
• 1991: VME64 (1014 Rev. D) was introduced and submitted to IEEE, raising the theoretical bus speed from 40 MBps to 80 MBps. The IEEE granted project authorization request (PAR) for P1014R (revisions to the VMEbus specification). Kim co-chaired the activity with Ray Alderman, technical director of VITA.
• 1992: Additional enhancements to VMEbus (A40/D32, Locked Cycles, Rescinding DTACK*, Autoslot-ID, Auto System Controller, and enhanced DIN connector mechanicals) required more work to complete this document. The VITA Technical Committee suspended work with the IEEE and sought accreditation as a standards developer organization (SDO) with the American National Standards Institute. The IEEE subsequently withdrew the original IEEE PAR P1014R. The VITA Technical Committee returned to using the public domain VMEbus C.1 specification as its base-level document, to which it added new enhancements. Kim carried out the tremendous undertaking of the document editing with assistance from Frank Hom, who created the mechanical drawings, and with exceptional contributions by each chapter editor.

Eike Waltz

Eike Waltz was a familiar face at VITA Technical Committee meetings in the early days. He was passionate about the mechanical aspects of VMEbus and served as the driving influence in many of the decisions made to guide the development of the mechanical specifications for VMEbus.

Eike received special recognition for his extensive contribution to the mechanical chapter (Chapter 7), which was incorporated into Revision C, ANSI/IEEE Std 1014-1987, and ANSI/VITA 1-1994 (S2011).

Eike was a technical sales manager at Schroff, an English company headquartered in Warwick, Rhode Island. He was a representative of the British Standards Institute committee on IEC 48D from 1976 to 1983. He also was a member of the IEEE P1014 (VMEbus) committee, as well as a coordinator for the central IEEE mechanical (IEC 297-3/3A) specification. Eike was instrumental in evangelizing VMEbus at the beginning of the standard’s development.

Key contributions

• 1984: Eike directed VMEbus mechanical design effort and documentation.

Tom Hall

Tom Hall spent numerous years in the VMEbus COTS industry selling and marketing military-spec VMEbus computer products to leading defense contractors and government departments throughout the world. He was a leading force in the development of technologies and major market segments while working at Plessey Microsystems, Radstone Technology, PEP Modular Computers, and Thales Computers.

Tom was responsible for the operation and major sales of Radstone Technology’s military products division. He also was president and CEO of PEP Modular Computers in Pittsburgh, where he was responsible for restructuring the German-based company’s U.S. operation. Tom later became the president and CEO of Thales Computers in Raleigh, North Carolina, a supplier of PowerPC and Pentium-based VME computing hardware, software, and system solutions.

Key contributions

• 1985: Tom promoted DIN connectors for defense applications.
• Started and shepherded the 1101.2 IEEE specification (conduction cooling) while working at Radstone Technology.
• 1997 to 2000: Member of VITA Board of Directors representing PEP Modular Computers.

PCI Mezzanine Cards

In the mid-1990s the embedded computing industry became entrenched in a heated debate over mezzanine card standards for 3U and 6U boards. At one point, 22 different proposals were on the table, not to mention at least as many more proprietary options. S-bus, advocated by Sun Microsystems, was gaining traction.

That all changed when a handful of industry-leading companies placed their bet on the emerging efforts led by Force Computers and Digital Equipment Corporation to marry S-bus mechanicals with the PCI bus.

In 1994 a number of companies joined together to launch the “We Agree … It’s PMC!” campaign, including Concurrent Technologies, Digital Equipment Corporation, Force Computers, Heurikon, Intel, Interphase, Mercury Computer Systems, Molex, Motorola Computer Group, Newbridge Microsystems, Schroff, Themis Computer, and Vigra. Architectures supporting PMC included VMEbus, VME64, Futurebus+, Multibus I, and Multibus II.

A PCI Mezzanine Card or PMC is a printed circuit board manufactured to the IEEE P1386.1 standard (chaired by VITA Technologies Hall of Famer Wayne Fischer). This standard combines the electrical characteristics of the PCI bus with the mechanical dimensions of the Common Mezzanine Card or CMC format (IEEE 1386 standard, see Figure 1).

A PMC can have up to four 64-pin bus connectors. The first two (P1 and P2) are used for 32-bit PCI signals; a third (P3) is needed for 64-bit PCI signals. An additional bus connector (P4) can be used for non-specified I/O signals. In addition, arbitrary connectors can be supplied on the front panel or bezel.

The PMC standard defines which connector pins are used for which PCI signals. It also defines the optional 64 P4 connector pins for use of arbitrary I/O signals.

Carrier cards that accept PMCs are usually made in the Eurocard format, which includes single-, double-, and triple-height VMEbus cards, CompactPCI cards, and more recently, VPX cards. One PMC fits on a standard 3U carrier card, while 6U models (typical for VMEbus cards) can carry up to two PMCs. Low-profile motherboards also can take advantage of the PMC architecture.

The PMC specification evolved into Processor PMC (PrPMC), which added extensions so the PMC could act as a bus master, making it possible for it to be the host processor card in a system.

Key milestones

• 1994: PMC (IEEE P1386.1) emerged out of efforts led by Force Computers and Digital Equipment Corporation to combine S-bus mechanicals with the PCI bus.
• 1994: DEC demonstrates PMC on an Alpha VME board.
• 2000: PMC P4 (ANSI/VITA 35) provides pin assignments for PMC P4 connector to VME P0 and P2 connectors.
• 2001: Conduction-Cooled PMC (ANSI/VITA 20) – Defines the mechanical requirements for compliance with conduction-cooled PMC modules.
• 2003: PrPMC (ANSI/VITA 32) – Incorporates a set of extensions to the PMC standard, which creates a new class of PrPMC cards.
• 2003: PCI-X for PMC and PrPMC (ANSI/VITA 39) – Integrates the PCI-X bus capability from PCI bus to PMC-based products.
• 2008: XMC: Switched Mezzanine Card base specification was introduced, bringing switch fabric interconnection to mezzanine cards for 3U and 6U.

VME64

VMEbus started on its path to significant performance improvements while still remaining backwards compatible with legacy systems with the introduction of the VME64 concept. In 1989, John Peters of Performance Technologies developed the initial concept of VME64: multiplexing address and data lines (A64/D64) on the VMEbus. The concept was demonstrated the same year and submitted to the VITA Technical Committee in 1990 as a performance enhancement to the VMEbus specification.

Key milestones

• 1989: John Peters and Bill Mahussen (Performance Technologies) developed the use of 64-bit multiplexed block transfer (MBLT) cycles and presented the VME64 concept to the VITA Technical Committee.
• 1990: Newbridge Microsystems released DARF 64 VME64 silicon.
• 1990: Performance Technology won the BUSCON Product of the Year award for VME64.
• 1991: VME64 (1014 Rev. D) was introduced and submitted to IEEE, raising the theoretical bus speed from 40 MBps to 80 MBps. The IEEE granted project authorization request (PAR) for P1014R (revisions to the VMEbus specification). Kim co-chaired the activity with Ray Alderman, technical director of VITA.
• 1992: Additional enhancements proposed to the VME64 specification were placed in VITA subcommittee: the VME64 Extensions Document. Two other activities began in late 1992: (1) VMEbus Board-Level Live Insertion specifications (BLLI), and (2) VMEbus System-Level Live Insertion with fault tolerance (VSLI).
• 1992: Newbridge Microsystems marketed the SCV64 single-chip VME64 interface.
• 1993: VITA subcommittees completed VME64.
• 1994: VERO Electronics offered a VME64 backplane.
• 1994: VME64 (ANSI/VITA 1) became the first VITA specification to receive ANSI approval. It defines the main body of the VMEbus specification and includes both 32- and 64-bit usage models.
• 1996: IP I/O Mapping to VME64x (ANSI/VITA 4.1) was approved, defining the pin assignments from IP modules to the VME64x P0 and P2 connectors.
• 1997: VME64 Extensions (ANSI/VITA 1.1) was approved as an extension to the VME64 specification, including the 160-pin connector, geographical addressing, and added power pins.
• 1997: VME64x 9U x 400 mm Format (ANSI/VITA 1.3) – Defines a 9U x 400 mm board layout for use within the VMEbus framework.
• 1998: VMEbus International Physics Association (VIPA, which includes CERN, Fermilab, and labs in Japan) rolled out VME64 Extensions for Physics (ANSI/VITA 23), which defines a series of recommended practices for the use of VMEbus in the physics community.
• 2000: Keying for Conduction-Cooled VME64x (ANSI/VITA 1.6) was approved for VMEbus technology.
• 2003: Gigabit Ethernet on VME64x Backplanes (ANSI/VITA 31.1) – Defines a pin assignment and interconnection methodology for implementing a 10/100/1000BASE-T Ethernet switched network on a VME64x backplane.

2eSST – ANSI/VITA 1.5-2003 (R2009)

This specification is an extension of the ANSI/VITA 1-1994, VME64, and ANSI/VITA 1.1-1997, VME64x specifications. It defines a transfer protocol based upon source-synchronous concepts that permits the VMEbus to operate at rates to at least 320 MBps. As technology improves, this rate can be extended to higher levels. The 2eSST specification emerged out of the MBLT and 2eVME concepts that extended the performance of VMEbus data transfers. Figure 2 compares the VME64 and 2eSST standards.

Thales Computers designed the Alma2e bridge supporting the 2eSST protocol in 2002. Tundra Semiconductor, working with Motorola, brought the Tsi148 PCI/X-to-VME2eSST bridge to market in 2004, making the 2eSST protocol available to the entire industry. Concepts exist to enhance VME2eSST that could increase performance to more than 1 GBps.

The 2eSST protocol requires low skew between signals and monotonic rising and falling edges on the signals. To meet these requirements, limited length backplanes, special backplane topologies, and/or enhanced transceivers are required. The specification calls for enhanced bus transceivers with controlled rise and fall times, tightly defined thresholds, low part to part skew, and low-voltage transistor-transistor logic (LVTTL) levels. During the development of this standard, specific transceivers were developed to meet these requirements.

As a source-synchronous protocol, the performance of 2eSST is determined not by the propagation delay from source to destination, but by skew – the variation in propagation delay through the drivers, backplane, and receivers. As the skew decreases, system bandwidth can increase. In theory, a source-synchronous protocol is virtually unlimited in its potential transfer rate. This standard provides for transfer rates of 160, 267, and 320 MBps with a 21-slot backplane. New transfer rates can be defined as the technology improves.

In developing the 2eSST protocol, several important objectives were considered:

• Maximize performance: Performance was the driving impetus for this new protocol. To meet this objective, the protocol was designed to ensure that all devices involved in the transfer would operate as fast as possible.
• Minimize complexity: The 2eSST protocol was designed to minimize the amount of logic that would be required to implement the protocol.
• Minimize application limits: The 2eSST protocol can be used in 3U, 6U, and 9U environments.
• Maintain compatibility: The 2eSST protocol was designed to be compatible with legacy VMEbus products.

Key milestones

• 1996: 2eVME protocol was proposed for VMEbus, allowing data transfers on both clock edges, thus doubling the VMEbus bandwidth.
• 2003: 2eSST (ANSI/VITA 1.5) – Defines VME protocol that allows data transfers up to 320 MBps.