The original specification was driven by the need to provide a 2.5 Gbps channel for PCI Express, but also encompassed other high-speed interconnects such as Serial ATA (SATA) and 10 Gigabit Ethernet. The latter was provided for by using the XAUI standard, implemented on a “fat pipe” with each of four lanes running at 2.5 Gbps. Over time and driven by technology evolution in the commercial marketplace, PCI Express has seen upgrades to Gen2 at 5 Gbps and then Gen3 at 8 Gbps. With each new generation, connector vendors and board manufacturers have risen to the challenge, employing more rigorous signal integrity models and design standards to keep pace with the technology.
More recently the challenge was thrown down by 10 Gigabit Ethernet, when the Intel Xeon Processor D released with two ports native to the device. The catch was that this capability used the 10GBASE-KR standard instead of XAUI, requiring a single pair in each direction to carry 10 Gbps. This transition from the “fat pipe” with four pairs in each direction to the “ultra-thin pipe” with a single pair in each direction has pushed the envelope again. The nature of the VPX and OpenVPX specifications means that this new technology can be absorbed without the large-scale changes of previous architectures.
Each successive improvement in capability at the hardware level drives greater performance at the system level. As customers seek to exploit their data to facilitate better decisions, the combination of ever-faster data rates and higher levels of processing density is allowing system designers to bring new functionality to the end user. The Intel Xeon Processor D represents both elements of this technological progression with its high-speed interfaces, including 10 Gigabit Ethernet, PCI Express Gen3 and SATA 6 Gbps, and its multicore Xeon architecture which includes built-in hardware virtualization and storage extensions.
The multicore nature of the Xeon D processor lends itself well to applications, which require processing and analysis of vast quantities of data, such as radar and sonar. The PCI Express Gen3 interfaces mean that systems can be integrated with higher-performance sensors, as well as with offload capabilities such as field-programmable gate array (FPGA) or general-purpose computing on graphics processing units (GPGPU), leading to more sophisticated analysis on-platform, close to the sensor.
Different systems have different size, weight, and power (SWaP) goals; for some, the need is to produce the same result with lower SWaP, while for others it is to provide greater capabilities within the same SWaP constraints. The hardware virtualization features of the Xeon D processor mean that multiple legacy applications can be condensed onto a single platform; this reduction of several legacy boards into a single slot not only make a system lighter, but could also pave the way for greater functionality in the newly vacated slots!
The storage extensions of the Xeon D mean that the architecture is well placed to be used in on-platform server architectures, offering storage capability, and potentially additional processing resources for systems throughout the platform. This consolidation of resources into a server may allow for lower overall SWaP across the platform if individual systems don’t require their own high-performance processing and storage.
VPX platforms can leverage the Xeon D architecture’s capabilities to improve security and efficiency of the network. To simplify the implementation of distributed computing at the edge of the network, fog computing enables secure and interoperable data exchanges between fog subsystems containing high performance edge node applications communicating with each other on a local area network (LAN), and other nodes and subsystems that are connected over a wide area network (WAN). In order to optimize both processing overhead and network bandwidth efficiency, fog computing enables the edge devices to be configured so that only “data of interest” is forwarded to the WAN.
Leading this technological evolution is the ADLINK VPX3010 processor blade with 12-core Intel Xeon Processor D-1500 SoC, which implements Intel’s new micro-server architecture to introduce the high performance computing power formerly limited to larger form factors into embedded environments. This VPX processor blade includes dual 10G-KR with up to three 1G Ethernet ports latest platform aimed at meeting the rugged and standards-based requirements of today’s military and aerospace applications.
With products like ADLINK’s VPX3010, (Figure 1) system designers now have greater capability to collect, store, analyze, and share data, and more scope to convert that data into good, timely decisions. VPX is at the heart of this evolution, and will continue to be an important driver for systems designers well into the future.
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