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  Articles  DÉJÀ VU – THE UBIQUITY OF VITA 57
Articles

DÉJÀ VU – THE UBIQUITY OF VITA 57

Matt Burns, SamtecMatt Burns, Samtec—August 23, 20230
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Every city has its own character, but every city also has so much in common.

Recently I was walking through the central business district of a major Midwestern city. I was struck by how so much was unique – museums, restaurants, local sports teams, boutique hotels, parks, trails, local watering holes, etc.

On the other hand, I also had a bit of déjà vu. It seems everywhere I looked I saw McDonald’s, Starbucks, Chipotle, and other popular national restaurants. Some may say that’s a bad thing, but sometimes it’s nice to know you can get a cheeseburger or burrito that tastes the same in Portland, ME as it does in Portland, OR.

What does this have to do with VITA 57, you may wonder? I am struck by the ubiquity of VITA 57 FMC and FMC+ interfaces.

What does that mean, you ask? It wasn’t that long ago that system designers relied on PCI Mezzanine Card (PMC) and Switched Mezzanine Card (XMC) standards for I/O expansion via daughter cards, mezzanine modules, or add-on cards. However, PMC and XMC were not originally configured for FPGAs.

Connector designs to meet high-speed needs

So, the FPGA vendors took it upon themselves to develop high-speed I/O expansion bus specifications for their development cards.  The FPGA vendors loved the design flexibility and scalability of PMC and XMC add-on cards, but more was needed to support the multi-gigabit transceivers becoming available on FPGAs.

One option proposed and developed by Altera (now Intel PSG) was the High Speed Mezzanine Card (HSMC) Specification. HSMC defined an electromechanical interface for a high-speed add-on card targeted for FPGA development kits. (Sound familiar?) Interoperability of add-on cards from multiple manufacturers was the goal. It would have been great if the FPGA industry adopted HSMC, but …

On the other side of Silicon Valley, a group of engineers at Xilinx (now AMD Xilinx) also recognized the need for a high-speed I/O expansion bus specification. Xilinx and its partners – other FPGA vendors, end-users, interconnect manufacturers and the like – decided an industry standard specification instead of a vendor-specific standard would likely be adopted by the fast-growing FPGAs industry as a whole.

More stories

VITA Standards Organization activity updates

December 14, 2015

Editor’s Foreword: Livin’ la Vida MOSA!

May 24, 2023

VITA 57.4: FMC+

December 19, 2018

VSO working groups roundup

October 8, 2013

Enter the creation of VITA 57.1 FMC.

The flexibility of FMC

VITA 57.1 FMC defines the electro-mechanical interface, standard mezzanine card form factor, connectors, and modular interface to an FPGA carrier card. Decoupling the I/O interfaces from the FPGA simplifies I/O interface module design while maximizing carrier card reuse.

VITA 57.1 FMC specifies two connector options linking the FPGA carrier card and mezzanine card. The low pin count (LPC) connectors offer 160 pins in a 4×40 array. They also provide 68 single-ended signals (or 34 differential pairs). The high pin count (HPC) connectors offer 400 pins in a 10×40 array. They also provide 160 single-ended signals (or 80 differential pairs), 10 MGTs running at 10 Gbps and additional clocks.

FMC’s flexibility offers many benefits. These include sustained implementation and deployment of new technologies. FMC also allows for more efficient prototyping and a faster time to market for FPGA-based systems.

Improved Performance with FMC+

VITA 57.4 FMC+ provided an update to VITA 57.1. Fully released in July 2018, VITA 57.4 FMC+ was designed to expand upon the already popular FMC standard while avoiding the hassle of implementation into existing systems.

FMC+ provides improved performance, faster data rates, and additional I/O, while utilizing the same footprint as FMC. Along with backwards compatibility with legacy FMC systems, FMC+ proves to be a stress-free improvement for any FPGA developer already using FMC.

A new FMC+ connector — high speed pin count (HSPC) — offers 560 pins in a 14×40 array, has 24 MGTs, and supports high-performance 28 Gbps FPGA transceivers. FMC+ also supports an optional, secondary connector — high-speed pin count extension (HSPCe) — which contains 80 pins in a 4×20 array and an additional 8 MGTs (for a total of 32).*

Figure 1 – Samtec VITA 57.4 FMC+ Connectors

Other connectors that support FMC and FMC+ are readily available as well. This includes modules that help to simplify connections from FPGAs/SoCs to industry-standard multimode fiber optic cables as well as ones that provide an easy-to-use loopback option for testing low-speed and high-speed multi-gigabit transceivers on any FPGA development board or FPGA carrier card.

So it really is déjà vu – VITA 57 is everywhere, from VITA 57.1 and 57.4 compliant modules to extender cards that increase board-to-board spacing on any FPGA development board or carrier card and loopback cards for testing low-speed and high-speed multi-gigabit transceivers on any FPGA development board or FPGA carrier card.  It is a standard that continues to evolve with the industry.

*Samtec provides many solutions that help FPGA developers evaluate and prototype FMC and FMC+ systems.

FMC
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