Moore’s Law is getting some serious push-back by the atoms that make up transistors. As IC geometrics shrink below “deep sub-micron” down to 65nm and tomorrow’s 45nm line widths, punch through and leakage currents become the dominant term in the equation. Electrons like to tunnel through the gate into the substrate instead of moving across the typical FET as in a normal CMOS transistor. This breakdown path plays havoc with the normal transitor operation, and becomes the gating item (pun intended) to achieving smaller transistors, increased IC density, and speed.
AMD and IBM, working together for many years on fundamental IC development, presented papers today at the International Electron Device Meeting (IEDM) in San Francisco describing the use of immersion lithography to produce ultra low-K dielectrics. The lower the dielectric constant K, the less chance of capacitive tunneling between the gate channel to the substrate – this lowers IC leakage currents and Moore’s Law is happy again.
