SAN DIEGO, CA – April 3, 2008 – Space Micro Inc. has recently completed development of their high data rate codec IC under a contract from the Air Force Research Lab (AFRL) in Rome, NY. ASIC devices were received by Space Micro in March from their silicon foundry and are now under test and evaluation. This is a 2-year SBIR Phase II contract with a value of $750,000. The research and development supports high data rate communications and particularly targets the DoD’s Transformational Communication Architecture Satellite (TSAT) program. The device is designed to be radiation hard to above100 krads (Si), and enables correction of errors in high-speed communication channels.
Mr. David Czajkowski, Chief Operating Officer commented, “This high data rate chip development uses advanced forward error correction algorithms and was previously demonstrated using an FPGA prior to implementation in a CMOS silicon ASIC.”
The new high data rate ECC chip is one of multiple technology development projects that Space Micro is currently developing for AFRL and NASA. The data rate of this initial chip is currently 2.5 Gbps; the architecture supports a rate of10 Gbps. The chip design uses Radiation Hardened By Design (RHBD) techniques. Forward error correction is achieved using a novel combination of Reed-Solomon and Turbo FEC coding techniques.
About Space Micro Inc.
Founded in 2002 as a satellite technology research and development company, Space Micro Inc. is a leader in taking technologies from the commercial sector and applying these to meet the needs of the Space, Aerospace, Military, and Domestic Security markets. Space Micro is a pioneer in providing radiation-hardened by design solutions for advanced electronic systems and microelectronics, including the development of the worlds fastest small space computers such as the Proton200kTM. Other Space Micro innovations include the Proton300K™; TTMR™; H-CORE™ and Radsite™. Space Micro is an employee-owned company based in San Diego, CA, USA.
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