The VME-to-PCI bridge is implemented in an FPGA for flexible VME-to-PCI mapping and to allow future updates and upgrades. The base address of the i4400 is configurable by DIP-switches. The i4400 VME to PCI bridge is mapped in Standard (A24) I/O space of the VMEbus. Each PMC site has its own software configurable base address in Extended (A32) I/O space. The DIP-switches are accessible for configuration even when both modules are mounted.
The i4400 features flexible rear I/O according to ANSI/VITA 35-2000. All 64 rear I/O signals from PMC site 1 are routed to VME P2. Using optional 5-row VMEbus connectors 46 rear I/O signals from PMC site 2 are routed to VME P2. Using the optional VME64x P0 connector all 64 rear I/O signals from PMC site 2 are available.
As an option the i4400 provides conduction cooling ribs according to ANSI/VITA 20-2001.
The interrupt controller on the i4400 has an interrupt vector register for each PCI-module. If a module is able to generate its own vector, the i4000 simply passes the interrupt request to the VMEbus. Interrupts for each PMC site can be masked separately. The level on which an interrupt is issued to the VMEbus, is software selectable.
On the front of the i4400 is a 7-segment display indicating the boot-status during FPGA boot sequence. Afterwards it can be used by the user for status information.
