The development of the standards
VPX fills the need for modular serial structure with robust performance and also specifies interfaces between plug-in modules and chassis for products intended for use in harsh environments. VPX combines the latest connector and packaging technology with innovative bus and serial fabric technology, resulting in lower pin count, reduced power requirements, and smaller chip/board space. For its part, VITA 48 specifies the mechanical or cooling interface between plug-in and housing, while VITA 65 defines the electrical interface between plug-in module and backplane and addresses the various requirements of the industry.
To ensure backward compatibility with existing hardware, the VPX specification includes regulations for 6U hybrid backplanes for VME64, VXS, and VPX boards. It supports a range of switched fabrics such as PCI Express, Serial RapidIO, and 10 Gbit Ethernet that can be configured in a variety of backplane topologies. VPX provides a powerful upgrade to switched-fabric technology for the processing of large amounts of data for users already deploying VME. Another advantage of VPX is its high overall I/O capacity: VPX offers 160 high-speed differential pairs, each nominally rated for a maximum performance of 10.3 Gbaud. Because of the high-speed signals, board and system designers must consider integrity analysis throughout the entire design phase of VPX products.
Complementary mechanical standards have been developed to further extend the benefits of VPX for rugged integrated systems. For example, the VITA 48 VPX Ruggedized Enhanced Design Implementation (REDI) standards specify alternative mechanical formats for extended functionality beyond the traditional IEEE 1101.1 and 1101.10 formats. This standard improves the cooling of embedded systems, including conductive cooling (fanless cooling via heat conduction) through larger and more efficient thermal interfaces and other cooling methods such as air and liquid cooling. Depending on the cooling method, the insertion height can vary. Because VPX enables a wide range of options, it’s important to get the exact specifications. That’s where the challenge comes in, as all the options have resulted in a wide variety of implementations. (Figure 1.)
[Figure 1 | Rugged half-ATR enclosure. HEITEC image.]
The VPX specification focuses primarily on the board level, but the wide variety of heterogeneous solutions has made it increasingly necessary to consider the system level in order to ensure interoperability; simplify adaptations; and reduce testing, cost, and risk. As a result of these efforts, OpenVPX (VITA 65) is the standard that defines VPX interoperability for integrated system environments with multiple modules as well as module and backplane designs including slot definition, while maintaining compatibility with VPX. The OpenVPX framework defines clear interoperability points required for module-to-module, module-to-backplane, and chassis integration; the backplane configuration tells the user which slot profiles are used, including information about data rate, routing topology, and implemented fabrics. Prior to the release of OpenVPX, an almost unlimited number of implementations with arbitrary slot assignments were in the market. Although they were implemented according to VITA 46, each system was so individual that board and backplanes could rarely be reused in other systems, even if they came from the same vendor.
OpenVPX has made it possible to develop open architectures and powerful embedded-hardware solutions as well as middleware layers. A number of recommendations exist to support the evaluation, prototyping, and development of VPX systems. By using the OpenVPX standard and architectural “toolbox” in combination with the existing connectivity, system developers can derive content and rules of the standard for their applications instead of starting from scratch. By limiting configurations, these profiles increase seamless interaction and reusability.
However, different types of applications typically require different system architectures with different backplane connectivity. OpenVPX supports central switching, distributed switching and master/slave topologies. Central switching uses dedicated switches in multiple topologies (e.g., Dual Star), whereas distributed switching includes full or partial network switching. The master-slave topology generally consists of a master host single-board computer (SBC) with attached slave PCIe fabric I/O cards (e.g., an SBC complex connected to I/O cards via PCIe).
OpenVPX offers a total of fifteen ANSI/VITA 65 6U backplane profiles, fourteen 6U module profiles, thirteen 3U backplane profiles and 22 3U module profiles to choose from. In addition, OpenVPX currently offers a range of recommended profiles for the selection of development enclosures, covering basic issues such as slot count, module type, module size, cooling, and power supply. (Table 1.)
[Table 1 | VPX performance overview. Courtesy HEITEC.]
Requirement profile and decision criteria
After defining the requirement profile for an application, a few decisions have to be made. First can be: Should 3U or 6U formats be used? If different modules – possibly from different manufacturers – are used, reliable system management may be required, which has some impact on the enclosure design. Factors that must be defined include slot and module payload profiles, as well as switch module profiles for the values to be achieved for data processing, throughput, and management. Pinouts, placements, and protocols should be precisely defined for the system design to eliminate errors from the start. Other questions that need asking: Are optical connectors in use or is an RF connector interface needed? Which baud rates are required by the application? What are the requirements for maintainability? Key decisions include cooling method, performance profile, backplane profile, protocols, and enclosure type.
An important factor in the choice of chassis is the cooling system. The power dissipation of VPX-based modules is often much higher than that of conventional VME or CompactPCI-based modules. Depending on the supply voltage, the power dissipation is usually around 100 watts, compared to most VME or CompactPCI modules, which run about 40 watts. There had been no standardization of power supply or cooling until the ANSI/VITA 65 OpenVPX standard came about; for the first time, specific criteria for power supply and the cooling of enclosures were defined, at a level usually two to four times the cooling capacity that typical VME or CompactPCI development chassis can handle for harsh environments. The ANSI/VITA 48.1 to 48.8 standards cover the different cooling methods such as air, liquid, or conduction cooling; also described is the wattage per plug-in module, components, and connectors.
Only a very small number of existing enclosures are capable of providing the required high cooling level of 18 CFM [cubic feet per minute] per slot, covering the vast majority of modules. It is up to the system developer to define the effort. For example, Intel Atom-based SBC modules typically dissipate 15 watts, while DSP-oriented multi-processor and FPGA [field-programmable gate array] modules often range from 100 to 150 watts. The cooling concept also plays an important role when configuring a module, for example, when adapting the plug-in modules to I/O requirements using mezzanine cards, which can be in conflict with the selected heat dissipation or airflow. Things to look at: The impact of rear-transition modules and their cabling requirements on the cooling scheme, whether cooling is possible on the rear panel at all, or whether the power has to be kept low there to avoid hot spots. Conduction-cooling enclosures dissipate the heat generated into the environment via cooling fins without a fan. If necessary, housings with liquid-cooled side panels must be used. Another factor: The influence of each respective measure on maintainability. Choosing the right concept from the beginning can save considerable money.
Another important criterion for the choice of housing is the performance profile. VPX enables the use of different power supplies, which reduces interoperability. OpenVPX recommends 5-volt and 12-volt power supplies, which should handle most applications. The choice of one or the other depends on the power consumption of the payload modules to be installed. Applications with a mix of 5-volt and 12-volt payload power profiles may require a modified power-supply configuration. The appropriate power profile is derived by taking the sum of the requirements of the selected payload modules. OpenVPX specifies up to 276 watts per slot in 3U and 768 watts per slot in 6U.
Selecting a backplane profile
The selection of a suitable backplane profile is also on the checklist. To wit: The backplane topology must support the application requirements and offer compatibility with the selected payload module profiles. Backplane profiles minimize size and cost and are designed for specific application types, such as master-slave control applications. They maximize data throughput in high-performance multiprocessing applications, efficiency for small numbers of slots in daisy chain and mesh topologies, and higher performance for large numbers of slots in central-switch topologies. More than one module profile may be compatible with a specific slot in a particular backplane profile. VITA 65 lists a single slot profile, but there are several other module profiles that are compatible.
Compatibility depends on the pins and signals connected in each respective backplane profile. All signals connected on the backplane must match defined signals that are the same type on the modules. They may have additional defined signals that are not connected on the backplane, but this is irrelevant for the compatibility of the module and the slot. For example, control-level and/or extension-level signals may be defined in the module profile that have no equivalent in the backplane profile. The module can be used in this slot, as long as the application has not connected these additional signals in the backplane. Fabric protocols and baud rates for modules at both ends of backplane profile connections must also match. To simplify this, all compatible module profiles for available OpenVPX standard backplanes have been identified. The standards thus cover the basics such as slot count, module type, module size, cooling, and power supply. HEITEC supports OpenVPX-compliant development chassis and backplanes, suitable for the vast majority of OpenVPX module profiles.
Ideally, the goal is facilitating general interchangeability between different versions and between manufacturers of similar systems. The Eurocard standard – according to IEC60297-3 or IEEE1101 – had the objective of standardizing the front-panel geometry and modularity of the plug-in units and defines the required dimensions and tolerances to ensure mechanical functional compatibility. This standard is based on the first card position, 3.27 mm from the left reference line of the opening; following card positions are based multiples of 5.08 mm (1HP) seen from the first card position. To allow for a uniform working distance between front panels, the total width of a front panel is usually 0.4 mm less than the nominal HP by 5.08 mm.
IEEE1101-1 and -11 extend the specifications and describe typical features for VME64x, CompactPCI, and PXI. Heights are nominally specified in U (multiples of 44.45 mm). A 2.5-mm-wide rim is provided at the top and bottom for mounting card guides and guide rails. Front panels and board sizes should be adapted if Eurocards with card holder are attached to the front panel. Strong tensile forces due to high pin counts require special handles and horizontal rails, while demanding applications also require electrostatic protection, which must be included in the mounting as well.
In the case of VPX, the VITA 48 standards specify the mechanical standard for 3U and 6U modules with air, conduction, or liquid cooling methods. The distance between the modules has been increased to 1 inch, compared to the 0.8 inch of the IEEE1101 standard. However, it is vital to consider that according to the definition in the VPX standards, there is an offset of the device to the front panel, which makes a mixed assembly of 4HP and 5HP VPX boards in one system difficult. Guide rails and moldings must be optimally adapted in this case.
Critical applications often require a two-stage maintenance scheme, so appropriate precautions must be taken during system design; that is, plug-in modules can be replaced in the field. The two levels refer to the organizational level – the area of application – as well as the depot level. Exchangeable plug-in modules must be repairable or exchangeable with a minimum of tools. EMC protection must be conceived to prevent damage during the handling (Figure 2). The time of intervention must be as short as possible, and the probability of errors must be minimized from the outset, e.g., by coding or the use of slot keying (exclusive slot assignment). Front panel connections may complicate maintenance, so the alternative of rear connections must be considered. Modules with several accessories may complicate the interchangeability of boards, so placement options must be carefully considered right from the start.
[Figure 2 | Mounted EMC spring with preparation for a restored card head for variable integration. Heitec image.]
For most complex applications that VPX is designed to handle, a holistic approach makes sense to prevent unwanted incompatibilities and minimize costs and risks. The interoperability enables scalable, robust and flexible solutions, performance migration when needed, as well as technology upgrades with lower obsolescence barriers. Especially for demanding applications in regulated markets, an individual concept is often the best solution. The system-level approach uses all advantages of the standard. HEITEC’s portfolio offers not only immediate access to the technology and immediate availability, but also all system design options including evaluation and service.
OpenVPX – Tutorial and Common Practices (Greg Rocco, MIT Lincoln Laboratory, 22nd January 2019.)