Accredited as an American National Standards Institute (ANSI) developer, VITA provides its members with the ability to develop and promote open technology standards.
The following standard has recently been ANSI and VITA ratified via public ballot:
- ANSI/VITA 67.3-2020: Coaxial Interconnect on VPX, Spring-Loaded Contact on Backplane
All published standards are available for download by VITA members and are posted at the online VITA Store for purchase by nonmembers.
VSO study and working group activities
Standards within VITA may be initiated through the formation of a study group and developed by a working group. A study group requires the sponsorship of one VITA member, while a working group requires sponsorship of at least three VITA members.
Several working groups have current projects underway. Here’s a roundup of these projects:
ANSI/VITA 42.0: XMC: Switched Mezzanine Card
Objective:The VITA 42.0 XMC standard defines a popular mezzanine card architecture using a PCIe interconnect to host carrier modules.
Status: The standard is due for its five-year review. The working group is reviewing revisions to bring the standard in line with current practice in related standards. A Signal Integrity (SI) appendix is being developed to include with the next release of the standard.
ANSI/VITA 46: VPX Baseline
Objective:The VITA 46.0 base standard defines physical features that enable high-speed communication in a compliant system.
Status: The standard is open for revisions. The working group is reviewing updates for compliance requirements and requirements for 12 V power.
ANSI/VITA 46.11: VPX System Management
Objective:The VITA 46.11 standard defines a system management architecture for VPX systems.
Status: The standard is due for its five-year review. Improvements based on feedback from the community are under consideration.
ANSI/VITA 48.0/48.2-2020: VPX REDI: Mechanical Base Standard/Conduction Cooling
Objective:The VITA 48 standards provide an overview of the associated plug-in units for air cooling, conduction cooling, and liquid-flow-thru (LFT) and spray cooling applications. Specific connector-mounting details are defined in VITA 46. The VITA 48 family of standards defines applicable detailed dimensions of key module and subrack interfaces. The implementations described in these standards are targeted for 3U and 6U form-factor boards on 0.85 and 1.00 centers. However, the packaging approach presented is applicable to boards with other form factors, different connector series, and alternate module pitches.
Status: The standards are being updated to allow for a 100 mm deep VPX module. The working group is developing a draft of the updates.
ANSI/VITA 48.4-2018: VPX REDI: Liquid-Flow-Thru Cooling
Objective:This standard establishes the mechanical design requirements for an LFT-cooled electronic VPX module.
Status: This working group is making revisions to the standard.
VITA 51.4: Reliability Component Derating
Objective:The goal of this working group is to develop a new component derating standard.
Status: This working group has joined forces with the IEEE to jointly develop this standard under IEEE-2818. A draft document has been developed.
This working group encourages industry participation and inputs for determining the appropriate derating considerations, specifically what derating levels your company typically uses. This information would help the working group find consensus derating levels for components that are useful for the industry.
ANSI/VITA 61: XMC 2.0
Objective:The VITA 61 XMC 2.0 standard, based upon VITA 42.0 XMC, defines an open standard for supporting high-speed, switched interconnect protocols on an existing, widely deployed form factor, but utilizing an alternate, ruggedized, high-speed mezzanine interconnector.
Status: The standard is due for its five-year review. Revisions to match VITA 42 and VITA 88 changes are in review.
VITA 62.1: Power Supply Front End for High-Voltage/3-Phase 3U Module
Objective:The VITA 62.1 standard describes requirements for building a high-voltage/3-phase/3U class front-end power-supply module that can be used to power a VPX chassis in the VITA 62 family of standards. The module will fit within the standard envelope defined for VPX modules in the VITA 48.0 standards.
Status: The working group is developing a draft document that is in review.
ANSI/VITA 65: OpenVPX Architectural Framework for VPX
Objective:The OpenVPX architectural framework standard is a living document that is regularly updated with new profile information and corrections.
Status: New profiles based on work with the Sensor Open Systems Architecture (SOSA) consortium are being developed.
VITA 66.5: Optical Interconnect on VPX – Hybrid Variant
Objective:This document describes an open standard for configuration and interconnect within the structure of VITA 66.0 enabling an interface compatible with VITA 46 containing blind-mate optical connectors with fixed contacts on the plug-in module and floating displacement on the backplane.
Status: The working group is developing the draft document.
ANSI/VITA 67.3: VPX: Coaxial Interconnect on VPX, Spring-Loaded Contact on Backplane
Objective:The VITA 67.3 standard defines an open standard for configuration and interconnect within the structure of VITA 67.0, enabling an interface compatible with VITA 46 containing multiposition blind-mate analog connectors with SMPM-style contacts having fixed contacts on the plug-in module and spring action on the backplane.
Status: The standard is open for revision.
VITA 68.2: VPX: Compliance Channel
Objective:This standard defines a VPX compliance channel, including common backplane performance criteria required to support multiple fabric types across a range of defined baud rates. This standard allows backplane developers to design a backplane that supports required bit-error rates (BER) for multiple fabric types. This also allows module developers to design plug-in modules that are interoperable with other modules when used with a compliant backplane.
Status: The document is in public ANSI/VITA review and ballot.
VITA 74.x: SpaceVNX
Objective:The VITA 74.x standards define a mechanical format for standardization of switched serial interconnects for small-form-factor applications
Status: The study group is gathering inputs for development of a potential standard for space platforms.
ANSI/VITA 78: SpaceVPX Systems
Objective:VITA 78 is an open standard for creating high-performance, fault-tolerant interoperable backplanes and modules to assemble electronic systems for spacecraft and other high-reliability (high-availability) applications. Such systems will support a wide variety of use cases across the aerospace community, including some nonspacecraft systems. This standard leverages the VPX standards family and the commercial infrastructure that supports these standards in nonspace applications.
Status: The standard is open for revisions. The documents have completed public ANSI/VITA review and are in the comment-resolution phase.
VITA 78.1: SpaceVPX Lite Systems
Objective:This standard leverages the work done on ANSI/VITA 78 to create a standard with an emphasis on 3U module implementations. The most significant change from SpaceVPX is to shift the distribution of utility signals from the utility-management module to the system-controller module to allow a radial distribution of supply power to up to eight payload modules.
Status: The working group has developed a draft document of the standard that is currently in working group ballot.
VITA 87: MT Circular Connectors
Objective:The VITA 87 MT circular connector standard defines a standard for circular connectors with optical MT. Circular connector shells are compliant to MIL-STD-38999. MT offer options for 12 or 24 fibers per MT and for physical contact or lensed MT.
Status: The working group is reviewing a draft document.
VITA 88: XMC+
Objective:The VITA 88 XMC+ standard defines an improved electrical/mechanical mezzanine connector for XMC applications. Mechanically, the proposed connector is compatible with VITA 42/61 footprints, achieving backward compatibility while offering improved mating/unmating forces. Electrically, speeds up to PCIe Gen 5 (32 Gbps) and maximum SI performance are supported.
Status: The working group is developing a draft document.