The New CAEN Mod. V1740 is a 1-unit wide VME 6U module housing a 64 Channel 12 bit 65 MS/s Flash ADC Waveform Digitizer with threshold Auto-Trigger capabilities.
The single ended analog input signal has a dynamic range of 2 Vpp (10 Vpp on request).
The DC offset of the input signal can be adjusted (for group of 8 channels) by a programmable 16bit DAC.
The modules feature a front panel clock/reference In/Out and a PLL for clock synthesis from internal/external references. This allows multi board phase synchronizations to an external clock reference or to a clock Digitizer master board.
The data stream is continuously written in a circular memory buffer. When the trigger occurs, the FPGA writes further N samples for the post trigger and freezes the buffer that can be read either via VME or via Optical Link. The acquisition can continue without dead time in a new buffer.
Each channel has a SRAM memory (from 192K to 1.5 M Samples/ch) with independent read-write access divided in buffers (1 ÷ 1024) of programmable size.
The trigger signal can be provided via the front panel input as well as via the VMEbus, but it can also be generated internally. The trigger from one board can be propagated to the other boards through the front panel Trigger Output.
The Modules VME interface is VME64X compliant and the data readout can be performed in Single Data Transfer (D32), 32/64 bit Block Transfer (BLT, MBLT, 2eVME, 2eSST) and 32/64 bit Chained Block Transfer (CBLT).
The boards houses a daisy chainable Optical Link able to transfer data at 80 MB/s, thus it is possible to connect up to eight ADC boards (512 ADC channels) to a single Optical Link Controller (Mod. A2818). Optical Link and VME access are internally arbitrated.
